In the Fall 2025 semester, I participated in a digital logic course design project where we designed and implemented a digital logic circuit using Verilog HDL. The project was part of the curriculum for the digital logic course at Southern University of Science and Technology (SUSTech).

In this project, we were tasked with designing a matrix calculator that could perform basic matrix operations such as addition, subtraction, multiplication and convolution. We used Verilog HDL to describe the behavior of the digital logic circuit and implemented it on an FPGA (Field-Programmable Gate Array) board.

We highlight the following features of our project:

• Matrix Operations: Our matrix calculator was capable of performing various matrix operations, including addition, subtraction, multiplication and convolution. This allowed us to demonstrate the versatility of our digital logic design and its ability to handle complex mathematical operations.
• Module Design: Our design was modular, allowing for easy expansion and modification of functionality. Each module was designed to be reusable and maintainable, contributing to the overall robustness of our system.
• User-Friendly Workflow: We developed a user-friendly workflow for interacting with the matrix calculator, including a simple interface for inputting matrices and selecting operations. This made it easier for users to utilize the functionality of our design without needing to understand the underlying digital logic. However, the interface was not used in the final defence due to time constraints.

The project earned 16.35/15 points in the final evaluation (with bonus). You can find the repo for this project at the repo link above.