Projects

This is a operation system for course design.

An education-oriented x86_64 operating system with multicore support, virtual memory, and preemptive scheduling.

SUSTech Computer Organization course design: a five-stage pipeline RISC CPU with caches, bus, DMA, and peripherals implemented in SystemVerilog on FPGA.

Designed and implemented a digital logic circuit using Verilog HDL.

A local-first desktop agent and CLI for personal development and research workflows, built with TypeScript and a monorepo architecture.

A modern, extensible rich-text editor built on ProseMirror with full TypeScript support, Markdown support, and LaTeX math.

I am currently assisting in the development of the proficiency assessment system for the Computer Science and Engineering (CSE) department at Southern University of Science and Technology (SUSTech), directed by Associate Professor Dr. Shiqi Yu.

Designing a private app for quant trading.